Refractory silicides have long been recognized as low resistivity gates and interconnects for integrated circuit structures in silicon devices. Now, gallium arsenide integrated circuits are being made with refractory silicide metallizations for self-aligned gates. Gallium arsenide integrated circuits are currently being utilized for VLSI structures, and conventional semiconductor fabrication techniques introduce certain problems when applied to gallium arsenide VLSI structures.
Conventional semiconductor processing utilizes an annealing step of 300 to 500 degrees Centigrade to activate the implanted source and drain regions. The manufacture of gallium arsenide circuits includes an annealing step of much higher temperatures, thereby requiring a greater thermal stability of the metal-gallium arsenide Schottky contact in order to withstand elevation to the higher temperatures, typically about 750 to 900 degrees Centigrade.
Previous work has concentrated on silicide composition in order to achieve the necessary thermal stability at the higher temperatures. Some recent articles indicative of this interest were published by
(1) Toyokazu Ohnishi and Naoki Yokoyama, of Fijitsu Laboratories Ltd., Atsugi, Workshop on Refractory Metals and Silicides for VLSI III, May 13-16, 1985, and (2) T. N. Jackson and J. F. DeGelormo, J. Vac. Sci. Technol., Vol. B3. November 1985, pp. 1676-1679.
Recently, experiments in gallium arsenide device fabrication have included polycrystalline silicon as the interconnection material in integrated circuits. Metallic silicides have been used in the place of the polycrystalline silicon as an interconnection material to overcome the disadvantages presented. The primary disadvantage is the relatively high minimum sheet resistivity of polysilicon of about 10 ohms per square. Titanium silicide, having a sheet resistance less than about one ohm per square, has been used to improve performance of large-scale integrated circuits employing MOSFET'S.
U.S. Pat. No. 4,545,116 issued Oct. 8, 1985 to Chi Lau discloses a method of forming titanium disilicide on silicon or polysilicon substrate in which a masking layer such as silicon dioxide is formed on a silicon slice and patterned to expose selected areas of the sliced surface. The slice is thereafter sputter-etched, followed by in situ deposition of single layer of titanium material. The silicon slice was then heated to convert the portion of the titanium layer in contact with the silicon to a titanium disilicide, and then the non-converted titanium was removed by a selective etchant.
Another problem presented in the fabrication of gates in gallium arsenide integrated circuits is the lack of adhesion of the gate to the substrate. In previous attempts to form gates on gallium arsenide, the Schottky diode quality has been relatively low due the adhesion problems. Scientists and engineers have been trying to solve this problem.
In order to ascertain the quality of devices produced, scientists look to two parameters, the ideality factor, and the I-V characteristics. The closer an ideality factor is to 1.0, the better the device. In terms of I-V characteristics, the barrier height measurement, which may also be referred to as the built-in potential, should be as close as possible to the theoretical Thermionic-Emission model. A value for this parameter of 0.80 eV is considered to be very good. Some of the best recently reported data for a tungsten silicide Schottky barrier on a gallium arsenide substrate had a measured ideality factor of 1.15 with a built-in potential of 0.80 eV after a 750 degree Centigrade annealing, as described by Shinoki, Shibatomi and Ishikawa in the IEEE Journal of Solid-State Circuits, Vol. SC-18, No. 5, October 1983, pp. 520-524.
Yet another problem presented when fabricating integrated circuits is the scaling down of interconnection and gate line widths both of which are required to achieve very large scale integration. Metallic silicides have proven to be advantageous in overcoming these problems because conventional silicidation is accompanied by out-diffusion which occurs during the reaction process. Silicon diffuses through the silicide layer into the metallic layer and reacts with the metal to form metallic silicide outside the original pattern. During further processing steps, the line width of the original pattern is thus destroyed. In extreme cases, bridging silicides between adjacent lines forms shorts by the out-diffused silicon. In the case of titanium silicide, this has caused a major problem in the preparation of VLSI circuit structures.
In summary, the above-mentioned problems of poor Schottky diode quality, adhesion, sheet resistivity, etc., become especially important in the fabrication of integrated circuits using gallium arsenide substrates. Devices of this type require superior characteristics of gate metallization. If such structures are to be used to provide a stable, high-temperature gate metallization in VLSI structures which exhibit optimum Schottky barrier heights and ideality factors, these problems must be overcome.